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最近在 看 systemverilog3.1a LRM,简直是 郁闷到家了 。每当讲到关键时刻 ,都会在来一句,……as verilog-2001.
下面有一段 英文 ,是讲关于systemverilog3.1a的 整数与逻辑literals的,不知道我这样翻译理解的对不对?
SystemVerilog adds the ability to specify unsized literal single bit values with a preceding apostrophe ( ' ), but
without the base specifier. All bits of the unsized value are set to the value of the specified bit. In a self-deter-
mined context these literals have a width of 1 bit, and the value is treated as unsigned.
'0, '1, 'X, 'x, 'Z, 'z // sets all bits to this value
(无论对于逻辑类型还是整数类型,)system-verilog增加了(只要)在数值前使用撇号,就可以定义一个
无符号类型的一位数值(的表述方式)。但基值不能被列出(即,只能默认为二进制值)。所无符号数的
比特形式都能置位(这种表示方式的)值。这样的表示方式自动的语境被识别为一位宽的数值,且当
作无符号类型来处理
还有,文中得一段目录 。还有包括上面这段话里的 “ literals”,怎么理解 ?我翻译成类型,对么?
目录: 2.2
Literal value syntax..........................................................................................................................4
2.3
Integer and logic literals ..................................................................................................................4
2.4
Real literals ......................................................................................................................................5
2.5
Time literals .....................................................................................................................................5
2.6
String literals....................................................................................................................................5
2.7
Array literals ....................................................................................................................................6
2.8
Structure literals ... |
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